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MCS-012 Computer Organisation and Assembly Language Programming Solved Assignment 2019-20

IGNOU BCA(2) / MCA(1) MCS-012 Computer Organisation and Assembly Language Programming Solved Assignment 2019-20

Course Code: MCS-012

Course Title: Computer Organisation and Assembly Language Programming

Assignment Number: MCA(2)/012/Assignment/ 2019-20

Maximum Marks: 100

Weightage: 25%

Last Dates for Submission: 15th October 2019 ( For July 2019 Session )

: 15th April 2020 ( For January 2020 Session )

There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answers to each part of the question should be confined to about 300 words. Make suitable assumption, if any.

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Q1. (Covers Block 1)

(a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11. Assuming the same machine to be used for execution of the following three consecutive instructions:

LOAD C: Loads the content of Memory location C into the Accumulator Register.

ADD B: Adds the content of memory location B in the Accumulator Register.

STORE A: Stores the content of Accumulator register AC in memory location A.

The following are the details about the instructions, data, and registers:

• Each word of memory is of 32 bits in length. Each instruction is also 32 bits long.
• The main Memory has 256 words.
• The three consecutive instructions, as shown above, starts from memory location (1F)h ; A is at location (FD)h and contains a value (1000)h, B is at location (FE)h and contains a value (FF3B)h and C is at location (FF)h and contains a value (2A2F)h.
• The AC, IR and MBR registers are of size 32 bits, whereas PC and MAR registers are of size 8 bits. The initial content of PC register is (1F)h

Draw the diagrams showing addresses and content of memory locations and Registers. Show how the content of memory locations and registers will change with the execution of the three instructions. Show all the addresses and values in hexadecimal notations. You must also perform the necessary arithmetic using signed 2’s complement notation and show the results indicating overflow, if any. Also explain the process of execution of the instructions.

(b) Perform the following conversion of numbers:

i) Decimal (3412454512) 10 to binary and hexadecimal ii) Hexadecimal (FEDCBA9) h into Octal. iii) String “In file name % means blank.” into UTF 8 iv) Octal (7766432) O into Decimal

(c) Assuming that inverse is represented as ‘, simplify the following Boolean functions:

F= ((A’ + B)’ + (A’+B’)’)’

(d) Simplify the following function using K-map: F(A, B, C, D) = Σ (0, 2, 6, 8, 10, 14)

Draw the circuit using NAND gates.

(e) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction if the value of A is 1111 and B is 1100. You must list all the bit values including Cin and Cout and overflow condition.

(f) Explain the functioning of a 2× 1 Multiplexer. You must draw its truth table and explain its logic diagram with the help of an example input.

(g) Assume that a data value 1111 was received as 1011. Explain how use of Hamming’s Error-Correcting code will send this data value from source and correct error at the destination.

(h) Explain functioning of S-R flip flop with the help of logic diagram, characteristic table and excitation table.

(i) Explain the functioning of Asynchronous and Synchronous counter. Explain how they are different from each other.

(j) Differentiate between fixed point numbers and floating point numbers? Explain the representation for Zero in IEEE 754 single precision standard. Represent (-32.25)10 and (0.000125)10 in IEEE 754 single precision format.

Q2. (Covers Block 2)

(a) Reference Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of a 64×8 RAM. Also answer the following:

(i) How many data input and data output lines does this RAM needs? Explain your answer.

(ii)How many address lines are needed for this RAM? Give reason in support of your answer.

(b) A computer has 16 MB RAM and has a word size of 32 bits. It has cache memory having 16 blocks having a block size of 64 bits. Show how the main memory address (17F0AB) h will be mapped to cache address, if

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii)Two way set associative cache mapping is used.

You must clearly identify tag, index, main memory block address and offset, etc. in your answer.

(c) Explain the process of Interrupt handling and Return from interrupt with the help of a diagram. You must answer this question in your own words.

(d) Differentiate between the working of DMA and I/O processor. Explain the DMA configurations and I/O channel structures.

(e) Assume that a disk has 2000 tracks with each track having 256 sectors and each sector is of size 2M. A file having the name openUni.txt is of size 32 M. Assume that disk has 16 free – continuous clusters of 4 sectors each at different locations on the disk. How can this file be allotted space on the disk? Also, show the content of FAT after the space allocation to this file. You may make suitable assumptions. You may assume the cluster size as 4 sectors if needed.

(f) Explain the following giving their uses and advantages/disadvantages. (Word limit for answer of each part is 50 words ONLY)

(i) SCSI and IDE in the context of Interfaces

(ii) Scanner and its resolution

(iii) Scan codes in the context of keyboard

(iv) Access time on disks

(v) Virtual Memory

(vi) RAID level 0, 3 and 5

Q3. (Covers Block 3)

(a) A computer has a single-core processor having 16 General purpose registers and 4 additional special-purpose registers. The machine has 1MB RAM. The size of each register and memory word is 32 bits each. An instruction of the machine is of fixed length and is equal to one memory word. Each instruction of the machine can have two operands – one memory operand and second register operand (register operand can be in General purpose registers only). Memory operand either uses direct addressing or is an immediate operand; however, register operand can use either register direct or register indirect addressing. (Please note that if register operand uses indirect addressing, then stated register contains the address of the operand in the memory.) An instruction of a machine consists of operation code bits, two addressing mode bit, one register operand and one memory operand. The addressing mode bits specifies addressing mode as:

The special-purpose registers are – Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The first register of the General purpose registers can be used as Accumulator Register. The size of Integer operands on the machine is 32 bits and it may be assumed to be equal to size of accumulator register. In order to execute instructions, the machine has an additional Instruction Register (IR) of size 32 bits as each instruction is of this size. Perform the following tasks for the machine.

(i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also, indicate how many different operations can be coded for this machine. Give reasons in support of your answer.

(ii) Put some valid values in registers and memory locations and demonstrate examples of different addressing modes of this machine.

(iii) Assuming that the instructions are first fetched to Instruction Register (IR) and memory operands is brought to DR register; indirect operand is brought to Accumulator register; and result of operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required for fetch and execute cycles of an instruction which performs subtraction of two operands having addressing mode bits as 00. Please note that one of the operands is Indirect Register Operand and the second is a direct memory operand. Make and state suitable assumptions, if any.

(b) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8-bit registers and contain 11000011 and 11100101 respectively. What will be the values of select inputs, carry-in input, and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above)

(i) Add R1 and R2 with carry

ii) Decrement R1

(iii)Shift right R1 twice

(iv) AND R1 and R2

(c) What is the role of Control Signal in execution of an Instruction? Block 3, page number 68-70, explains the timing sequence for execution of ISZ instruction. Explain execution of an ADDITION instruction with the help of micro-operations and timing sequences.

(d) What is the role of micro-programmed Control Unit? How a micro-program is executed? Explain with the help of a diagram.

(e) List and explain the characteristics of RISC machines. A RISC machine has 256 registers out of which 64 registers are reserved for the Global variables and 64 for Instruction related tasks. This machine has been designed to have 12 registers for storing three input parameters, three output parameters and six local variables for a function call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for function/procedure calls. You must explain how the parameters will be passed when a function calls another function. How many levels of procedural calls, such a machine can support?

Q4. (Covers Block 4)

(a) Write a program using 8086 assembly Language (with proper comments) that accepts an input of ten characters from the keyboard and store them in the memory. It then converts all the lower case alphabets of this stored string to uppercase alphabets. Make suitable assumptions, if any.

(b) Write a program using 8086 assembly Language (with proper comments) that finds the sum and average of 10-byte numbers stored in two different arrays of size 5 each.

(c) Explain the following in the context of 8086 Microprocessor

(i) Use of Segment Registers

(ii) Use of Interrupts in Input/output

(iii).com and .exe programs

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There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words. Make suitable assumption, if any.

Q1. (Covers Block 1)

(a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11. Assuming the same machine to be used for execution of the following three consecutive instructions:

LOAD C ; Loads the content of Memory location C into the Accumulator Register. ADD B ; Adds the content of memory location B in the Accumulator Register.

STORE A ; Stores the content of Accumulator register AC in memory location A.

The following are the details about the instructions, data and registers:

•  Each word of memory is of 32 bits in length. Each instruction is also 32 bits long.
•  Main Memory has 256 words.
•  The three consecutive instructions as shown above starts from memory location (1F)h ; A is at location (FD)h and contains a value (1000)h, B is at location (FE)h and contains a value (FF3B)h and C is at location (FF)h and contains a value (2A2F)h.
•  The AC, IR and MBR registers are of size 32 bits, whereas PC and MAR registers are of size 8 bits. The initial content of PC register is (1F)h

Draw the diagrams showing addresses and content of memory locations and Registers. Show how the content of memory locations and registers will change with the execution of the three instructions. Show all the addresses and values in hexadecimal notations. You must also perform the necessary arithmetic using signed 2's complement notation and show the results indicating overflow, if any. Also explain the process of execution of the instructions.

(b) Perform the following conversion of numbers: 

i) Decimal (3412454512)10 to binary and hexadecimal

ii) Hexadecimal (FEDCBA9)h into Octal.

iii) String “In file name % means blank.” into UTF 8

iv) Octal (7766432) O into Decimal

(c) Assuming that inverse is represented as ', simplify the following Boolean functions: F= ((A' + B)' + (A'+B')')' (1)

(d) Simplify the following function using K-map: F(A, B, C, D) = Σ (0, 2, 6, 8, 10, 14) Draw the circuit using NAND gates. (2)

(e) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction, if the value of A is 1111 and B is 1100. You must list all the bit values including Cin and Cout and overflow condition. (1)

(f) Explain the functioning of a 2× 1 Multiplexer. You must draw its truth table and explain its logic diagram with the help of an example input. (2)

(g) Assume that a data value 1111 was received as 1011. Explain how use of Hamming's ErrorCorrecting code will send this data value from source and correct error at the destination. (2)

(h) Explain functioning of S-R flip flop with the help of logic diagram, characteristic table and excitation table. (2)

(i) Explain the functioning of Asynchronous and Synchronous counter. Explain how they are different from each other. (2)

(j) Differentiate between fixed point numbers and floating point numbers? Explain the representation for Zero in IEEE 754 single precision standard. Represent (-32.25)10 and (0.000125)10 in IEEE 754 single precision format.

Q2. (Covers Block 2)

(a) Reference Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of a 64×8 RAM. Also answer the following:

(i) How many data input and data output lines does this RAM needs? Explain your answer.

(ii)How many address lines are needed for this RAM? Give reason in support of your answer. 

(b) A computer has 16 MB RAM and has a word size of 32 bits. It has cache memory having 16 blocks having a block size of 64 bits. Show how the main memory address (17F0AB)h will be mapped to cache address, if

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii)Two way set associative cache mapping is used. You must clearly identify tag, index, main memory block address and offset etc. in your answer. 

(c) Explain the process of Interrupt handling and Return from interrupt with the help of a diagram. You must answer this question in your own words.

(d) Differentiate between the working of DMA and I/O processor. Explain the DMA configurations and I/O channel structures. (3)

(e) Assume that a disk has 2000 tracks with each track having 256 sectors and each sector is of size 2M. A file having the name openUni.txt is of size 32 M. Assume that disk has 16 free - continuous clusters of 4 sectors each at different locations on the disk. How can this file be allotted space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions. You may assume the cluster size as 4 sectors, if needed. (4)

(f) Explain the following giving their uses and advantages/disadvantages. (Word limit for answer of each part is 50 words ONLY) (6)

(i) SCSI and IDE in the context of Interfaces

(ii) Scanner and its resolution

(iii) Scan codes in the context of keyboard

(iv) Access time on disks

(v) Virtual Memory (vi) RAID level 0, 3 and 5

Q3. (Covers Block 3)

(a) A computer has a single core processor having 16 General purpose registers and 4 additional special purpose registers. The machine has 1MB RAM. The size of each register and memory word is 32 bits each. An instruction of the machine is of fixed length and is equal to one memory words. Each instruction of the machine can have two operands – one memory operand and second register operand (register operand can be in General purpose registers only). Memory operand either uses direct addressing or is an immediate operand; however, register operand can use either register direct or register indirect addressing. (Please note that if register operand uses indirect addressing, then stated register contains the address of the operand in the memory.) An instruction of a machine consists of operation code bits, two addressing mode bit, one register operand and one memory operand. The addressing mode bits specifies addressing mode as:

                                                                                  Addressing mode bit                                   Register Operand                                    Memory Operand

                                                                                               00                                                           Indirect                                                      Direct

                                                                                                01                                                           Direct                                                        Direct

                                                                                               10                                                           Indirect                                              Immediate Operand           

                                                                                               11                                                              Direct                                              Immediate Operand

The special purpose registers are - Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The First register of the General purpose registers can be used as Accumulator Register. The size of Integer operands on the machine is 32 bits and it may be assumed to be equal to size of accumulator register. In order to execute instructions the machine has an additional Instruction Register (IR) of size 32 bits as each instruction is of this size. Perform the following tasks for the machine.

(i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also indicate how many different operations can be coded for this machine. Give reasons in support of your answer.

(ii) Put some valid values in registers and memory locations and demonstrate examples of different addressing modes of this machine. (1)

(iii) Assuming that the instructions are first fetched to Instruction Register (IR) and memory operands is brought to DR register; indirect operand is brought to Accumulator register; and result of operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required for fetch and execute cycles of an instruction which performs subtraction of two operands having addressing mode bits as 00. Please note that one of the operand is Indirect Register Operand and the second is a direct memory operand. Make and state suitable assumptions, if any.

(b) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 11000011 and 11100101 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above) (2)

(i) Add R1 and R2 with carry

(ii) Decrement R1

(iii)Shift right R1 twice

(iv)AND R1 and R2

(c) What is the role of Control Signal in execution of an Instruction? Block 3, page number 68- 70, explains the timing sequence for execution of ISZ instruction. Explain execution of an ADDITION instruction with the help of micro-operations and timing sequence. (3)

(d) What is the role of micro-programmed control Unit? How a micro-program is executed? Explain with the help of a diagram. (2)

(e) List and explain the characteristics of RISC machines. A RISC machine has 256 registers out of which 64 registers are reserved for the Global variables and 64 for Instruction related tasks. This machine has been designed to have 12 registers for storing three input parameters, three output parameters and six local variables for a function call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for function/procedure calls. You must explain how the parameters will be passed when a function calls another function. How many levels of procedural calls, such a machine can support? (3)

Q4. (Covers Block 4)

(a) Write a program using 8086 assembly Language (with proper comments) that accepts an input of ten characters from the keyboard and store them in the memory. It then converts all the lower case alphabets of this stored string to uppercase alphabets. Make suitable assumptions, if any. (7)

(b) Write a program using 8086 assembly Language (with proper comments) that finds the sum and average of 10 byte numbers stored in two different arrays of size 5 each. (7) 10

(c) Explain the following in the context of 8086 Microprocessor (6)

(i) Use of Segment Registers

(ii) Use of Interrupts in Input/output

(iii).com and .exe programs

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8 thoughts on “IGNOU MCS-012 Study Material”

Please send me pdf material with diagrams

plz send me pdf material mca ebooks hindi and english

how to get old question papers solved.

plz send me PDF material

Pdf doesn’t show any diagram please fix this issue as soon as possible 🙏

in this material figure is not showing…

Have you received textbook with figures? Unbelievable carelessness from textbook makers!

Yes in my physical book there are diagrams, LOTS OF THEM

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IGNOU MCS-012 Previous Year Question Papers-Last 10 Years

• February 4, 2024

If you’re preparing for the  IGNOU MCS-012 Computer Organization and Assembly Language Programming  exam of BCA/BCAOL 2nd semester, and are looking for old exam question paper, then below you’ll find a link to download IGNOU MCS-012 Previous Year Question Papers. We have uploaded the last 10-years question paper, simply click on the link below to download.

MCS-1 2 Previous Paper Details

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IGNOU MCS-012 Computer Organization and Assembly Language Programming Question Paper Download

Are you trying to prepare for your IGNOU BCA MCS-012 Computer Organization and Assembly Language Programming exams but struggling to find the right resources? Look no further! In this article, we’ll provide you with a step-by-step guide on how to download IGNOU MCS-012 Computer Organization and Assembly Language Programming Question Paper and sample papers easily. Read on to learn more about where to find these resources and how you can use them to effectively prepare for your upcoming exams.

Introduction to IGNOU BCA MCS12

IGNOU BCA or Bachelor of Computer Applications is a three-year undergraduate course offered by the Indira Gandhi National Open University. The course has been designed to provide students with a strong foundation in computer applications.

The following steps will help you download IGNOU BCA MCS-012 question papers and sample papers easily:

• Visit the official website of IGNOU at www.ignou.ac.in.
• On the homepage, click on the ‘Student Zone’ tab and then select ‘Downloads’ from the drop-down menu.
• Now, under the ‘Question Papers’ section, select your programme i.e., ‘BCA’ and then choose your desired year and semester.
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Download Last 5 Year’s Question Paper on  MCS-012 

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The official IGNOU MCS-012 Computer Organization and Assembly Language Programming Previous question papers and sample papers can be found on the university website. However, these are not always easy to find. Here is a quick guide on how to download them:

• Go to the IGNOU website (ignou.ac.in) and click on the ‘Student Zone’ tab at the top of the page.
• On the next page, scroll down to the ‘Examination’ section and click on the ‘Downloads’ link.
• On the downloads page, scroll down to the ‘BCA’ section and click on the ‘Question Papers’ link.
• This will take you to a page with all of the available BCA question papers. You can either download them individually or as a ZIP file.

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• IGNOU MCS-012 Computer Organization and Assembly Language Programming Question Paper and Sample Papers can be downloaded from the official website of IGNOU.
• To download the papers, firstly visit the website and then click on the ‘Student Zone’ tab given at the top of the page.
• After that, select ‘Question Papers’ from the drop-down menu. Now, a list of all available question papers and sample papers will be displayed on your screen.
• You can either select the paper you want to download or can search for it by using the provided search box.
• Once you have found the paper, click on the ‘Download’ button given next to it. The paper will now start downloading automatically.
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It is always better to be prepared for exams in advance and IGNOU BCA Exams are no different. Here are some tips that will help you prepare for your exams:

• परीक्षा पैटर्न और पाठ्यक्रम समाधान: हर परीक्षा के लिए तैयार होना का पहला चरण परीक्षा पैटर्न और पाठ्यक्रम समझ है। जब आपको पता चलता है कि परीक्षा में कौनसे टॉपिक कवर होंगे, तो आप उसके हिसाब से तैयार शुरू कर सकते हैं।
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• मॉक टेस्ट अभ्यास करना: और एक महत्वपूर्ण टिप है मॉक टेस्ट अभ्यास करना, वास्तविक परीक्षा के पहले। ये आपको पता चलता है कि परीक्षा में कौनसे टाइप के प्रश्न पूछे जाएंगे और आपको आत्मविश्वास भी बढ़ाता है। ऑनलाइन बहुत सारे सैंपल पेपर और पिछले साल के प्रश्न पत्र उपलब्ध हैं जो आप इस उद्देश्य के लिए उपयोग कर सकते हैं।

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MCS-012 Computer Organisation and Assembly Solved Assignment 2018-2019

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Course Code : MCS-012 Course Title : Computer Organisation and Assembly Language Programming Assignment Number : BCA(2)/012/Assignment/2018-19 Maximum Marks : 100 Weightage : 25% Last Dates for Submission : 15th October, 2018 (For July, 2018 Session) 15st April, 2019 (For January, 2019 Session)

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There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words. Make suitable assumption, if any.

Question 1 (Covers Block 1) (a) What are fixed point numbers in a computer system? Why are negative fixed point numbers represented in complement form? Give examples of fixed point numbers (positive as well as negative) assuming the size of the notation to be 8 bits (including sign bit). Perform the following arithmetic operations using signed 2’s complement 8 bit representation. (Please note that the numbers given below are in decimal notation) i) Add –30 and –98 ii) Subtract –79 from 45 Please indicate overflow if it is occurs. Explain how have you identified the overflow? (2 Marks) (b) Perform the following conversion of numbers: i) Decimal (56789123)10 to binary and hexadecimal ii) Hexadecimal (ABCDEF0)H into Octal. iii) ASCII string “Subject: Computer %$ Sc.” into UTF 8 string iv) Octal (345123)O into Decimal (2 Mark) (c) Design a circuit for the following function: F(A, B, C, D) = Σ (2,3,4, 5, 10, 11, 12, 13) Draw the truth table. Use the Karnaugh’s map to design the circuit and draw it using AND, OR and NOT gates. (4 Marks) (d) What is the need of a parity bit? Explain with the help of an example. How many parity bits are needed to detect and correct a single bit error in a 8-bit data? Explain the process of correction of Single bit error with the help of an example which is not from your Unit. (4 Marks) (e) Design a two bit down counter (a sequential circuit). The counter states are 11, 10, 01, 00, 11, 10, 01, 00, 11…You should show the state table, state diagram, the k-map for circuit design and logic diagram of the resultant design using D flipflop or J-K flip flop. (4 Marks) (f) What is floating point number? What is the difference between Single precision and double precision floating point numbers? What is a representation for Zero in IEEE 754 single precision standard. Represent (-23456.05)10 and (0.00025)10 in IEEE 754 single precision format. (4 Marks) Question 2 (Covers Block 2) (a) A RAM has 1M rows each having 16 cells: (i) How many data input and data output lines does this RAM needs? Explain your answer. (ii) What is the capacity of RAM in bytes. (iii) How many address lines are needed for this RAM? Give reason in support of your answer. (2 Marks) (b) A computer has 1 MB RAM and has a word size of 16 bits. It has cache memory having 8 blocks having a block size of 32 bits. Show how the main memory address 0001 1001 1110 1101 0001 will be mapped to cache address, if (i) Direct cache mapping is used (ii) Associative cache mapping is used (iii)Two way set associative cache mapping is used. (4 Marks) (c) What is the need of DMA in a Computer? How is DMA different than that of Interrupt driven I/O technique? Assume that a new computer supports few bytes of input from multiple user’s, which of the three I/O techniques is most suitable for this computer? Justify your answer. (4 Marks) (d) Assume that a disk has 1000 tracks with each track having 64 sectors and each sector is of size 512 K. A file having the name bcamca.txt is of size 16 M. Assume that disk has four free continuous clusters of 8 sectors each. How can this file be given the space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions. You may assume the cluster size as 2 sectors, if needed. (4 Marks) (e) Explain the following giving their uses and advantages/disadvantages. (Word limit for answer of each part is 50 words ONLY) (6 Marks) (i) Memory Interleaving (ii) RAID (iii) IDE interface (iv) CAV and CLV in the context of disks (v) Passive and Active matrix display (vi) Advantages and disadvantages of Ink-jet printers Question 3 (Covers Block 3) (a) A computer has a single core processor having 8 General purpose registers and 8 additional special purpose registers. The machine has 64 KB RAM. The size of each register and memory word is 16 bits each. An instruction of the machine is of fixed length and is equal to two memory words. Each instruction of the machine has two operands – one memory operand and second register operand. Memory operand uses direct addressing; however, register operand can use either register direct or register indirect addressing. (Please note that if register operand uses indirect addressing, then stated register contains the address of the operand in the memory.) An instruction of a machine consists of operation code bits, One addressing mode bit and one register operand and one memory operand. The addressing mode bit specifies addressing mode as: Addressing mode bit Register Operand Memory Operand 0 Indirect Direct 1 Direct Direct Five of the special purpose registers perform the task as Program Counter (PC), Accumulator (AC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The size of Integer operands on the machine may be assumed to be of equal to size of accumulator register. In order to execute instructions the machine has an Instruction Register (IR) of size 32 bits as each instruction is of this size. Perform the following tasks for the machine. (i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also indicate how many different operations can be coded for this machine. Give reasons in support of your answer. (3 Marks) (ii) Put some valid values in certain registers and memory locations and demonstrate examples of different addressing modes of this machine. (1 Mark) (iii)Assuming that the instructions are first fetched to Instruction Register (IR) and memory operands is brought to DR register; indirect operand is brought to AC; and result of operation is stored in the AC register; write and explain the sequence of micro-operations that are required for fetch cycle and execute cycle of an instruction which performs addition of two operands having addressing mode bits as 0. Please note that one of the operand is Indirect Register Operand and the second is a direct memory operand. Make and state suitable assumptions, if any. (6 Marks) (b) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 01111011 and 10000100 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above) (2 Marks) (i) Subtract R2 from R1with borrow (ii) Exclusive OR of R1 and R2 (iii)Shift Left R1 twice (iv)Increment R1 (c) Explain the structure of Control Unit with the help of block diagram. What is the role of control signals in instruction execution? (3 Marks) (d) Explain the reasons of reducing complexity in a RISC machine. What are the advantages of using large register file in RISC? How RISC machine’s instruction pipelining different from other machine’s instruction pipelining? (2 Marks) (e) A RISC machine has 128 registers out of which 32 registers are reserved for the Global variables and 32 for Instruction related tasks. This machine has been designed to have 8 registers for storing two input parameters, two output parameters and four local variables for function call. Explain with the help of a diagram, how the overlapped register window can be implemented in this machine for function/procedure calls. You must explain how the parameters will be passed when a function calls another function. How many levels of calls such a machine can support? (3 Marks) Question 4 (Covers Block 4) (a) Write a program using 8086 assembly Language (with proper comments) that accepts four characters entered using the keyboard. It checks if all these characters are decimal digits. If all of them are decimal digits, then program calculates the equivalent hexadecimal value of the four digit number that has been input. The program then displays this hexadecimal number on the screen. Make suitable assumptions, if any. (7 Marks) (b) Write a program using 8086 assembly Language (with proper comments) that passes AL register value as parameter to a near procedure named DIVZERO, which checks if this passed AL value is zero or not. In case this value is ZERO program is terminated, otherwise same value is returned in AL register. Make suitable assumptions, if any. (7 Marks) (c) Explain the following in the context of 8086 Microprocessor (6 Marks) (i) The supported memory in 8086 is 1 MB whereas instruction offset is only 16 bits (ii) Processing of Interrupts using IVT (iii) Indirect addressing modes of 8086 microprocessor

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